計算機體係結構：量化研究方法（英文版·第5版） [Computer Architecture:A Quantitative Approach,Fifth Edition] 下載 mobi epub pdf 電子書 2024

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編輯推薦

　　《計算機體係結構：量化研究方法（英文版·第5版）》特點：
　　更新相關內容以覆蓋移動計算變革，並強調當今體係結構重要的兩個主題：存儲器層次結構和各種並行技術。
　　每章中的"Putting It All Together"小節關注瞭業界的各種技術，包括ARM Cortex-A8、Intel Core i7、NVIDIAGTX-280和GTX-480 GPU，以及一種Google倉庫級計算機。
　　每章都設計瞭常規主題：能力、性能、成本、可依賴性、保護、編程模型和新趨勢。
　　書中包括3個附錄，另外8個附錄可以在原齣版社網站在綫得到。
　　每章後都設置瞭由工業界和學術界專傢提供的經過更新的案例研究，以及與之配套的全新練習題。

內容簡介

　　《計算機體係結構：量化研究方法（英文版·第5版）》堪稱計算機係統結構學科的“聖經”，是計算機設計領域學生和實踐者的必讀經典。本書係統地介紹瞭計算機係統的設計基礎、存儲器層次結構設計、指令級並行及其開發、數據級並行、GPU體係結構、綫程級並行和倉庫級計算機等。
　　現今計算機界處於變革之中：移動客戶端和雲計算正在成為驅動程序設計和硬件創新的主流範型。因此在這個版中，作者考慮到這個巨大的變化，重點關注瞭新的平颱（個人移動設備和倉庫級計算機）和新的體係結構（多核和GPU），不僅介紹瞭移動計算和雲計算等新內容，還討論瞭成本、性能、功耗、可靠性等設計要素。每章都有兩個真實例子，一個來源於手機，另一個來源於數據中心，以反映計算機界正在發生的革命性變革。
　　本書內容豐富，既介紹瞭當今計算機體係結構的研究成果，也引述瞭許多計算機係統設計開發方麵的實踐經驗。另外，各章結尾還附有大量的習題和參考文獻。本書既可以作為高等院校計算機專業高年級本科生和研究生學習“計算機體係結構”課程的教材或參考書，也可供與計算機相關的專業人士學習參考。

作者簡介

　　John L.Hennessy，斯坦福大學校長，IEEE和ACM會士，美國國傢工程研究院院士及美國科學藝術研究院院士。Hennessy教授因為在RISC技術方麵做齣瞭突齣貢獻而榮獲2001年的Eckert-Mauchly奬章，他也是2001年Seymour Cray計算機工程奬得主，並且和本書另外一位作者David A. Patterson分享瞭2000年John von Neumann奬。
　　David A. Patterson 加州大學伯剋利分校計算機科學係主任、教授，美國國傢工程研究院院士，IEEE和ACM會士，曾因成功的啓發式教育方法被IEEE授予James H. Mulligan，Jr.教育奬章。他因為對RISC技術的貢獻而榮獲1995年IEEE技術成就奬，而在RAID技術方麵的成就為他贏得瞭1999年IEEE Reynold Johnson4R息存儲奬。2000年他John L. Hennessy分享瞭John yon Neumann奬。

精彩書評

　　“本書之所以成為永恒的經典，是因為它的每一次再版都不僅僅是更新補充，而是一次全麵的修訂，對這個激動人心且快速變化領域給齣瞭及時的信息和獨到的解讀。對於我來說，即使已有二十多年的從業經曆，再次閱讀本書仍自覺學無止境，感佩於兩位卓越大師的淵博學識和深厚功底。”
　　——Luiz Andre Barroso，Google公司

目錄

Foreword
Preface
Acknowledgments
Chapter 1 Fundamentals of Quantitative Design and Analysis
1.1 Introduction
1.2 Classes of Computers
1.3 Defining Computer Architecture
1.4 Trends in Technology
1.5 Trends in Power and Energy in Integrated Circuits
1.6 Trends in Cost
1.7 Dependability
1.8 Measuring, Reporting, and Summarizing Performance
1.9 Quantitative Principles of Computer Design
1.10 Putting It All Together: Performance, Price, and Power
1.11 Fallacies and Pitfalls
1.12 Concluding Remarks
1.13 Historical Perspectives and References Case Studies and Exercises by Diana Franklin

Chapter 2 Memory Hierarchy Design
2.1 Introduction
2.2 Ten Advanced Optimizations of Cache Performance
2.3 Memory Technology and Optimizations
2.4 Protection: Virtual Memory and Virtual Machines
2.5 Crosscutting Issues: The Design of Memory Hierarchies
2.6 Putting It All Together: Memory Hierachies in the ARM Cortex-AS and Intel Core i7
2.7 Fallacies and Pitfalls
2.8 Concluding Remarks: Looking Ahead
2.9 Historical Perspective and References Case Studies and Exercises by Norman P. Jouppi, Naveen Muralimanohar, and Sheng Li

Chapter 3 nstruction-Level Parallelism and Its Exploitation
3.1 Instruction-Level Parallelism: Concepts and Challenges
3.2 Basic Compiler Techniques for Exposing ILP
3.3 Reducing Branch Costs with Advanced Branch Prediction
3.4 Overcoming Data Hazards with Dynamic Scheduling
3.5 Dynamic Scheduling: Examples and the Algorithm
3.6 Hardware-Based Speculation
3.7 Exploiting ILP Using Multiple Issue and Static Scheduling
3.8 Exploiting ILP Using Dynamic Scheduling, Multiple Issue, and Speculation
3.9 Advanced Techniques for Instruction Delivery and Speculation
3.10 Studies of the Limitations oflLP
3.11 Cross-Cutting Issues: ILP Approaches and the Memory System
3.12 Multithreading: Exploiting Thread-Level Parallelism to Improve Uniprocessor Throughput
3.13 Putting It All Together: The Intel Core i7 and ARM Cortex-AS
3.14 Fallacies and Pitfalls
3.15 Concluding Remarks: What's Ahead?
3.16 Historical Perspective and References Case Studies and Exercises by Jason D. Bakos and Robert R Colwell

Chapter4 Data-Level Parallelism in Vector, SIMD, and GPU Architectures
4.1 Introduction
4.2 Vector Architecture
4.3 SIMD Instruction Set Extensions for Multimedia
4.4 Graphics Processing Units
4.5 Detecting and Enhancing Loop-Level Parallelism
4.6 Crosscutting Issues
4.7 Putting It All Together: Mobile versus Server GPUS and Tesla versus Core i7
4.8 Fallacies and Pitfalls
4.9 Concluding Remarks
4.10 Historical Perspective and References Case Study and Exercises by Jason D. Bakos

Chapter 5 Thread-Level Parallelism
5.1 Introduction
5.2 Centralized Shared-Memory Architectures
5.3 Performance of Symmetric Shared-Memory Multiprocessors
……
Chapter6 Warehouse-Scale Computers to Exploit Request-Level and Data-Level Parallelism
Appendix A Instruction Set Principles
Appendix B Review of Memory Hierarchy
Appendix C Pipelining: Basic and Intermediate Concepts

精彩書摘

The pressure of both a fast clock cycle and power limitations encourages limited size for first-level caches. Similarly， use of lower levels of associativity can reduce both hit time and power， although such trade-offs are more complex than those involving size.
The critical timing path in a cache hit is the three-step process of addressing the tag memory using the index portion of the address， comparing the read tag value to the address， and setting the multiplexor to choose the correct data item if the cache is set associative. Direct-mapped caches can overlap the tag check with the transmission of the data， effectively reducing hit time. Furthermore， lower levels of associativity will usually reduce power because fewer cache lines must be accessed.
Although the total amount of on-chip cache has increased dramatically with new generations of microprocessors， due to the clock rate impact arising from a larger L1 cache， the size of the L1 caches has recently increased either slightly or not at all. In many recent processors， designers have opted for more associativity rather than larger caches. An additional consideration in choosing the associativity is the possibility of eliminating address aliases; we discuss this shortly.
One approach to determining the impact on hit time and power consumption in advance of building a chip is to use CAD tools. CACTI is a program to estimate the access time and energy consumption of alternative cache structures on CMOS microprocessors within 10% of more detailed CAD tools. For a given minimum feature size， CACTI estimates the hit time of caches as cache size varies， associativity， number of read/write ports， and more complex parameters. Figure 2.3 shows the estimated impact on hit time as cache size and associativity are varied.
……

前言/序言

計算機體係結構：量化研究方法（英文版·第5版） [Computer Architecture:A Quantitative Approach,Fifth Edition] 下載 mobi epub pdf txt 電子書 格式

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